Publications and Downloads

2022

• DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit [abstract]

  R. S. Rajarathnam, M. B. Alawieh, Z. Jiang, M. Iyer and D. Z. Pan, "DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit," 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 2022. [bibtex]

  Abstract:
  Modern Field Programmable Gate Arrays (FPGAs) are large-scale heterogeneous programmable devices that enable high performance and energy efficiency. Placement is a crucial and computationally intensive step in the FPGA design flow that determines the physical locations of various heterogeneous instances in the design. Several works have employed GPUs and FPGAs to accelerate FPGA placement and have obtained significant runtime improvement. However, with these approaches, it is a non-trivial effort to develop optimized and algorithmic-specific kernels for GPU and FPGA to realize the best acceleration performance. In this work, we present DREAMPlaceFPGA, an open-source deep-learning toolkit-based accelerated placement framework for large-scale heterogeneous FPGAs. Notably, we develop new operators in our framework to handle heterogeneous resources and FPGA architecture-specific legality constraints. The proposed framework requires low development cost and provides an extensible framework to employ different placement optimizations. Our experimental results on the ISPD'2016 benchmarks show very promising results compared to prior approaches.
  BibTeX:
  

  @inproceedings{dreamplacefpga-aspdac2022,
  author={Rajarathnam, Rachel Selina and Alawieh, Mohamed Baker and Jiang, Zixuan and Iyer, Mahesh and Pan, David Z.},
  booktitle={27th Asia and South Pacific Design Automation Conference (ASP-DAC)}, 
  title={DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit}, 
  year={2022},
  volume={},
  number={},
  pages={300-306},
  numpages = {7},
  doi={10.1109/ASP-DAC52403.2022.9712562},
  month = jan
  }
  

2021

• End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression [abstract]

  A. Na, M. Ibrahim, M. Hall, A. Boutros, A. Mohanty, E. Nurvitadhi, V. Betz, Y. Cao & J. Seo. (2021). End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. In Proceedings of the Int. Conf on Field Programmable Logic and Applications (FPL). [bibtex]

  Abstract:
  Object detection is an important computer vision task, with many applications in autonomous driving, smart surveillance, robotics, and other domains. Single-shot detectors (SSD) coupled with a convolutional neural network (CNN) for feature extraction can efficiently detect, classify and localize various objects in an input image with very high accuracy. In such systems, the convolution layers extract features and predict the bounding box locations for the detected objects as well as their confidence scores. Then, a non-maximum suppression (NMS) algorithm eliminates partially overlapping boxes and selects the bounding box with the highest score per class. However, these two components are strictly sequential; a conventional NMS algorithm needs to wait for all box predictions to be produced before processing them. This prohibits any overlap between the execution of the convolutional layers and NMS, resulting in significant latency overhead and throughput degradation. In this paper, we present a novel NMS algorithm that alleviates this bottleneck and enables a fully-pipelined hardware implementation. We also implement an end-to-end system for low-latency SSD-MobileNet-V1 object detection, which combines a state-of-the-art deeply-pipelined CNN accelerator with a custom hardware implementation of our novel NMS algorithm. As a result of our new algorithm, the NMS module adds a minimal latency overhead of only 0.13 microseconds to the SSD-MobileNet-V1 convolution layers. Our end-to-end object detection system implemented on an Intel Stratix 10 FPGA runs at a maximum operating frequency of 350 MHz, with a throughput of 609 frames-per-second and an end-to-end batch-1 latency of 2.4 ms. Our system achieves 1.5x higher throughput and 4.4x lower latency compared to the current state-of-the-art SSD-based object detection systems on FPGAs.
  BibTeX:
  

  @inproceedings{hpipe-nms-fpl21,
  author = {Na, A. and Ibrahim, M. and Hall, M. and Boutros, A. and Mohanty, A. and Nurvitadhi, E. and Betz, V. and Cao, Y. and Seo, J.},
  title = {End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression},
  year = {2021},
  isbn = {},
  booktitle = {Proceedings of the International Conference on Field-Programmable Logic and Applications},
  pages = {1–8,
  numpages = {8},
  month = aug
  }
  

• DO-GPU: Domain Optimizable Soft GPUs

  R. Ma, J. Hsu, T. Tan, E. Nurvitadhi, R. Vivekanandham, A. Dasu, M. Langhammer, & D. Chiou. (2021). DO-GPU: Domain Optimizable Soft GPUs. In Proceedings of International Conference on Field-Programmable Logic and Applications (FPL).

• Pigasus: Efficient Handling of Input-Dependent Streaming on FPGAs [pdf]

  Z. Zhao. (2021). Pigasus: Efficient Handling of Input-Dependent Streaming on FPGAs. PhD Thesis, ECE, Carnegie Mellon University.

• Fluid: Raising the Level of Abstraction for FPGA Accelerator Development Without Compromising Performance [pdf]

  J. Melber. (2021). Fluid: Raising the Level of Abstraction for FPGA Accelerator Development Without Compromising Performance. PhD Thesis, ECE, Carnegie Mellon University.

• We Need Kernel Interposition over the Network Dataplane [abstract] [pdf]

  Sadok, H., Zhao, Z., Choung, V., Atre, N., Berger, D. S., Hoe, J. C., Panda, A., & Sherry, J. (2021). We Need Kernel Interposition over the Network Dataplane. In Proceedings of the Workshop on Hot Topics in Operating Systems. Ann Arbor, MI, USA. ACM, New York, NY, USA. ACM, New York, NY, USA. [bibtex]

  Abstract:
  Kernel-bypass networking, which allows applications to circumvent the kernel and interface directly with NIC hardware, is one of the main tools for improving application network performance. However, allowing applications to circumvent the kernel makes it impossible to use tools (e.g., tcpdump) or impose policies (e.g., QoS and filters) that need to interpose on traffic sent by different applications running on a host. This makes maintainability and manageability a challenge for kernel-bypass applications. In response, we propose Kernel On-Path Interposition (KOPI), in which traditional kernel dataplane functionality is retained but implemented in a fully programmable SmartNIC. We hypothesize that KOPI can support the same tools and policies as the kernel stack while retaining the performance benefits of kernel bypass.
  BibTeX:
  

  @inproceedings{Sadok2021,
  author = {Sadok, Hugo and Zhao, Zhipeng and Choung, Valerie and Atre, Nirav and Berger, Daniel S. and Hoe, James C. and Panda, Aurojit and Sherry, Justine},
  title = {We Need Kernel Interposition over the Network Dataplane},
  year = {2021},
  isbn = {},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  booktitle = {Proceedings of the Workshop on Hot Topics in Operating Systems},
  pages = {1–6},
  numpages = {6},
  month = jun,
  series = {{HotOS}~'21}
  }
  

• FlexScore: Quantifying Flexibility

  T. Tan, E. Nurvitadhi, A. Dasu, M. Langhammer, & D. Chiou. (2021). FlexScore: Quantifying Flexibility. IEEE Computer Architecture Letters.

• System Level Tradeoffs Between ASIC and FPGA Accelerators

  T. Tan. (2021). System Level Tradeoffs Between ASIC and FPGA Accelerators. PhD Thesis, ECE, University of Austin.

2020

• Achieving 100Gbps Intrusion Prevention on a Single Server [abstract] [pdf] [slides] [video] [opensource]

  Zhao, Z., Sadok, H., Atre, N., Hoe, J., Sekar, V., & Sherry, J. (2020). Achieving 100Gbps Intrusion Prevention on a Single Server. In Proceedings of the 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI). Berkeley, CA, USA: USENIX Association. [bibtex]

  Abstract:
  Pigasus is an 100Gbps Intrusion Detection and Prevention System that can inspect network traffic by checking against 10K+ rules with the support of 100K+ concurrent connections. Pigasus is implemented on a single server using one FPGA-based SmartNIC with a few CPU cores, saving hundreds of cores compared with CPU-only approach. The Github repository contains the FPGA RTL code, CPU full matcher code and scripts for RTL simulation, synthesis build and hardware onboard test.
  BibTeX:
  

  @inproceedings {258923,
  author = {Zhipeng Zhao and Hugo Sadok and Nirav Atre and James C. Hoe and Vyas Sekar and Justine Sherry},
  title = {Achieving 100Gbps Intrusion Prevention on a Single Server},
  booktitle = {14th {USENIX} Symposium on Operating Systems Design and Implementation ({OSDI} 20)},
  year = {2020},
  isbn = {978-1-939133-19-9},
  pages = {1083--1100},
  url = {https://www.usenix.org/conference/osdi20/presentation/zhao-zhipeng},
  publisher = {{USENIX} Association},
  month = nov,
  }