FPGA’s poor time-to-solution is a primary reason why FPGAs have not yet achieved widespread adoption. Time-to-solution includes all of the time to generate all of the desired results, including development time, compile time, debug time, refinement time, and the production runs. Most current FPGA programmability tools focus on a subset of time-to-solution, such as the initial development, but none that we are aware of addresses the entire time-to-solution lifecycle. For example, FPGA compile times are a significant blocker to time-to-solution, because of low productivity due to the round-trip time between starting a compile and being able to debug. Developing in simulation is too slow and expensive. Our approach to this problem is based on a continuum of approaches that, when used together, reduce time-to-solution of existing monolithic approaches that can only be partially optimized for different conditions. That continuum contains at least standard processors, FPGA-based processor overlays with different tradeoffs, and FPGA-based dedicated circuits. Different solutions on the continuum would optimize for (i) software-like development times, including compile times, (ii) better than software observability and debuggability, and (ii) superior run times. The solution will target heterogeneous platforms and be data-movement-aware, enabling the user to find the sweet spot for the specific requirements at any given time.
RV2 PIs: Derek Chiou and Franz Franchetti