News and Events
February 2022 | Intel’s Corporate Research Council recognizes Crossroads Center PIs Sherry, Sekar and Hoe with 2021 Outstanding Researcher Awards for their work on the Pigasus FPGA-Accelerated Intrusion Detection and Prevention System. Pigasus inspects 100k+ concurrent connections against 10k+ SNORT rules at 100 Gbps in a single server form factor by handling common-case processing… read more
February 2022 | Intel’s Corporate Research Council recognizes Crossroads Center PIs Sherry, Sekar and Hoe with 2021 Outstanding Researcher Awards for their work on the Pigasus FPGA-Accelerated Intrusion Detection and Prevention System. Pigasus inspects 100k+ concurrent connections against 10k+ SNORT rules at 100 Gbps in a single server form factor by handling common-case processing in an Intel FPGA SmartNIC. Pigasus was developed by former CMU PhD student Dr. Zhipeng Zhao in his dissertation on efficient acceleration of irregular, data-dependent stream processing. Today, Pigasus is a focus application driver for many technologies under research by the Crossroads Center. Pigasus has gained broad interest as an open-sourced project with a growing academic and industrial user and developer community. (Read Less)
December, 2021 | Mohamed Ibrahim successfully defended his MASc thesis at the University of Toronto. His thesis detailed enhancements to the HPIPE FPGA-based CNN accelerator to perform object detection and to span multiple FPGAs for higher performance. Mohamed developed an automatic partitioning algorithm that allows HPIPE accelerators to achieve higher parallelism by… read more
December, 2021 | Mohamed Ibrahim successfully defended his MASc thesis at the University of Toronto. His thesis detailed enhancements to the HPIPE FPGA-based CNN accelerator to perform object detection and to span multiple FPGAs for higher performance. Mohamed developed an automatic partitioning algorithm that allows HPIPE accelerators to achieve higher parallelism by spanning multiple FPGAs. Both performance models and deployment on a multi-Stratix-10 system in James Hoe’s group at CMU showed near-linear speedup as the FPGA count increased. Mohamed will join Intel’s Deep Learning Accelerator team in February. (Read Less)
December 2021 | The paper “Specializing for Efficiency: Customizing AI Inference Processors on FPGAs,” by by Andrew Boutros, Vaughn Betz (University of Toronto) and Eriko Nurvitadhi (Intel) received the “Third Paper Award” from the IEEE International Conference on Microelectronics. This work showed that specializing NPU accelerators to workload classes improves performance by 9% to 35% while simultaneously reducing resource usage … read more
December 2021 | The paper “Specializing for Efficiency: Customizing AI Inference Processors on FPGAs,” by by Andrew Boutros, Vaughn Betz (University of Toronto) and Eriko Nurvitadhi (Intel) received the “Third Paper Award” from the IEEE International Conference on Microelectronics. This work showed that specializing NPU accelerators to workload classes improves performance by 9% to 35% while simultaneously reducing resource usage by 23% to 44%. Andrew is currently augmenting the SystemC NPU model to investigate dividing the NPU into modular latency-insensitive components; this will enable investigation of Crossroads FPGA architecture ideas that include linking components and accelerators with a (latency-insensitive) NoC. (Read Less)
November 4th, 2021 | Pigasus Developers Meeting met for the first time on November 4, 2021. Pigasus Developers Meeting is a forum for all users and developers of Pigasus to come together to jointly coordinate the continuing development of the open-sourced Pigasus FPGA accelerated network intrusion detection and prevention system. The Pigasus 2.0 release was announced in this meeting. You are welcome to sign up to the Pigasus Mailing List.
November 4th, 2021 | Pigasus Developers Meeting met for the first time on November 4, 2021. Pigasus Developers Meeting is a forum for all users and developers of Pigasus to come together to jointly coordinate the continuing development of the open-sourced Pigasus FPGA accelerated network intrusion detection and prevention system. The Pigasus 2.0 release was announced in this meeting. You are welcome to sign up to the Pigasus Mailing List. (Read Less)
November 4th, 2021 | A new release of Pigasus FPGA accelerated network intrusion detection and prevention system is available at http://www.pigasus-ids.org. Pigasus 2.0 is a refactoring of the original Pigasus into a disaggregated design where parameterized IPs are connected by standardized abstract connections. In conjunction with FLUID, a high-level end-user could generate specifically tuned Pigasus instances (scaling performance, tuning to new bottlenecks, multi-FPGA mapping, etc.). More advanced users can modify or introduce custom IPs to derive new designs.
November 4th, 2021 | A new release of Pigasus FPGA accelerated network intrusion detection and prevention system is available at http://www.pigasus-ids.org. Pigasus 2.0 is a refactoring of the original Pigasus into a disaggregated design where parameterized IPs are connected by standardized abstract connections. In conjunction with FLUID, a high-level end-user could generate specifically tuned Pigasus instances (scaling performance, tuning to new bottlenecks, multi-FPGA mapping, etc.). More advanced users can modify or introduce custom IPs to derive new designs. (Read Less)
October 2021 | VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling” has received the 2021 best paper award from the ACM Transactions on Reconfigurable Technology and Systems (TRETS) journal; Crossroads researchers Vaughn Betz (University of Toronto) and Jason Luu (Intel) both contributed to this paper. The Crossroads project continues to enhance VTR to improve result quality and to enable new architecture investigations such as embedded NoCs and more-than-2D FPGA systems.
October 2021 | VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling” has received the 2021 best paper award from the ACM Transactions on Reconfigurable Technology and Systems (TRETS) journal; Crossroads researchers Vaughn Betz (University of Toronto) and Jason Luu (Intel) both contributed to this paper. The Crossroads project continues to enhance VTR to improve result quality and to enable new architecture investigations such as embedded NoCs and more-than-2D FPGA systems. (Read Less)
August 27th, 2021 | The center’s PIs and students, along with invited external attendees including Intel, VMware and our research collaborators, got together to exchange progress and discuss findings. (Agenda with presentation abstracts) The student workshop is a bi-annual event for the center.
August 27th, 2021 | The center’s PIs and students, along with invited external attendees including Intel, VMware and our research collaborators, got together to exchange progress and discuss findings. (Agenda with presentation abstracts) The student workshop is a bi-annual event for the center. (Read Less)
July 28th, 2021 | Crossroads student Joseph Melber successfully defends his PhD thesis entitled “Fluid: Raising the Level of Abstraction for FPGA Accelerator Development Without Compromising Performance.” An important artifact from Melber’s thesis is the Fluid IP composition framework. Fluid stipulates an abstracted interface architecture to facilitate the authoring of highly reusable accelerator component IPs … read more
July 28th, 2021 | Crossroads student Joseph Melber successfully defends his PhD thesis entitled “Fluid: Raising the Level of Abstraction for FPGA Accelerator Development Without Compromising Performance.” An important artifact from Melber’s thesis is the Fluid IP composition framework. Fluid stipulates an abstracted interface architecture to facilitate the authoring of highly reusable accelerator component IPs for an NoC-enabled FPGA fabric. Furthermore, Fluid provides a high-level description framework for designers to author expressive and maintainable descriptions of the infrastructural context enclosing the accelerator component composition. Pigasus 2.0 will adopted the Fluid framework to support flexible composition of parameterized component stages and virtualization of platform and communication. (Read Less)
July 8th, 2021 | Crossroads student Zhipeng Zhao successfully defends his PhD thesis entitled “Pigasus: Efficient Handling of Input-Dependent Streaming on FPGAs.” In this thesis, Zhao exploits FPGAs’ programmability in an innovative design style that optimizes for traffic-dependent common-case behavior while relegating rare—often more complicated—behaviors to low-cost slow-path handling. The thesis … read more
July 8th, 2021 | Crossroads student Zhipeng Zhao successfully defends his PhD thesis entitled “Pigasus: Efficient Handling of Input-Dependent Streaming on FPGAs.” In this thesis, Zhao exploits FPGAs’ programmability in an innovative design style that optimizes for traffic-dependent common-case behavior while relegating rare—often more complicated—behaviors to low-cost slow-path handling. The thesis investigates both compile-time and runtime re-adaptation to expected and experienced traffic profile. An important artifact from Zhao’s thesis is the Pigasus IDS/IPS. Besides being a major application focus of Crossroads RV1, it has also emerged as an important design driver for all remaining RVs. The Pigasus team is launching a monthly Users Group Meeting to coordinate future developments of the Pigasus IPS/IDS. (Read Less)
July 2021 | A full system simulator for Crossroads 3D FPGAs has been created and verified by Andrew Boutros (University of Toronto). The simulator is written in SystemC, and allows arbitrary SystemC modules representing design components to connect to embedded networks on chip using standard AXI interfaces. The SystemC modules can represent modules implemented in traditional FPGA… read more
July 2021 | A full system simulator for Crossroads 3D FPGAs has been created and verified by Andrew Boutros (University of Toronto). The simulator is written in SystemC, and allows arbitrary SystemC modules representing design components to connect to embedded networks on chip using standard AXI interfaces. The SystemC modules can represent modules implemented in traditional FPGA fabric, embedded (hard) accelerators, memory implemented in a base die, off chip interfaces, and more. The Network on Chip is highly parameterizable in terms of topology, router design, link width and more, and both functionality (data transported) and timing (latency, congestion) are simulated. This simulator allows rapid what-if analysis of architecture ideas that incorporate different NoCs, embedded memory and accelerators in a multi-die Crossroads system. Please contact Andrew Boutros, Mohamed Ibrahim and Vaughn Betz (University of Toronto). (Read Less)
May 18, 2021 | The Intel/VMware Crossroads 3D-FPGA Academic Research Center launches a YouTube Channel for its seminar series.
May 18, 2021 | The Intel/VMware Crossroads 3D-FPGA Academic Research Center launches a YouTube Channel for its seminar series. (Read Less)
May 2021 | “Koios – A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research” has been accepted for publication at the upcoming Int. Field Programmable Logic and Applications (FPL) Conference. This Koios benchmark suite was developed in collaboration by the University of Texas at Austin (Aman Arora, Dr. Lizy John and her group) and University of Toronto Crossroads Center researchers… read more
May 2021 | “Koios – A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research” has been accepted for publication at the upcoming Int. Field Programmable Logic and Applications (FPL) Conference. This Koios benchmark suite was developed in collaboration by the University of Texas at Austin (Aman Arora, Dr. Lizy John and her group) and University of Toronto Crossroads Center researchers (Andrew Boutros and Vaughn Betz). Koios designs are supported by the completely open source ODIN-II + ABC + VPR CAD flow, and hence can be retargeted at new FPGA architecture ideas. The Koios designs are larger, faster, and more deeply pipelined than current open-source FPGA benchmark suites, making them better test cases for future FPGA architecture ideas. Please contact Andrew Boutros, Mohamed Ibrahim and Vaughn Betz (University of Toronto). (Read Less)
May 2021 | “End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression” has been accepted for publication at the upcoming Int. Field Programmable Logic and Applications (FPL) Conference. Mohamed Ibrahim and Andrew Boutros collaborated with Anupreetham of Arizona State University, and Eriko Nurvitadhi of Intel to develop a higher performance architecture… read more
May 2021 | “End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression” has been accepted for publication at the upcoming Int. Field Programmable Logic and Applications (FPL) Conference. Mohamed Ibrahim and Andrew Boutros collaborated with Anupreetham of Arizona State University, and Eriko Nurvitadhi of Intel to develop a higher performance architecture for single shot object detection (SSD) using FPGAs. The architecture combines the HPIPE CNN architecture that uses customized hardware for each layer of a CNN to achieve high performance with a new, FPGA-friendly non-maximum suppression (NMS) technique to remove overlapping object bounding boxes. Please contact Andrew Boutros, Mohamed Ibrahim and Vaughn Betz (University of Toronto). (Read Less)
April 23, 2021 | The Intel/VMware Crossroads 3D-FPGA Academic Research Center launches its seminar series with Joe Melber as the inaugural speaker presenting his PhD dissertation work on a service-oriented memory abstraction and infrastructure for computing FPGAs.
April 23, 2021 | The Intel/VMware Crossroads 3D-FPGA Academic Research Center launches its seminar series with Joe Melber as the inaugural speaker presenting his PhD dissertation work on a service-oriented memory abstraction and infrastructure for computing FPGAs. (Read Less)
April 2021 | Shashank Obla successfully brought up an early prototype of a new dynamic runtime system that makes use of PR and services technologies to enable runtime composable application deployment on a Bittware 520N-MX (Stratix 10 MX2100). Please contact Shashank Obla and James C. Hoe (Carnegie Mellon University).
April 2021 | Shashank Obla successfully brought up an early prototype of a new dynamic runtime system that makes use of PR and services technologies to enable runtime composable application deployment on a Bittware 520N-MX (Stratix 10 MX2100). Please contact Shashank Obla and James C. Hoe (Carnegie Mellon University). (Read Less)
March 2021 | The paper “We Need Kernel Interposition over the Network Dataplane” is accepted by the 18th Workshop on Hot Topics in Operating Systems (HotOS XVIII). In the paper, Crossroads PIs and students, along with other university and industry collaborators, propose Kernel On-Path Interposition (KOPI), in which traditional kernel dataplane functionality is retained… read more
March 2021 | The paper “We Need Kernel Interposition over the Network Dataplane” is accepted by the 18th Workshop on Hot Topics in Operating Systems (HotOS XVIII). In the paper, Crossroads PIs and students, along with other university and industry collaborators, propose Kernel On-Path Interposition (KOPI), in which traditional kernel dataplane functionality is retained but implemented in a fully programmable FPGA-based SmartNIC. Please contact Hugo Sadok and Justine Sherry (Carnegie Mellon University). (Read Less)
March 2021 | The paper “FlexScore: Quantifying Flexibility” was accepted to Computer Architecture Letters. In the paper, Crossroads PIs and students, along with Intel co-authors Eriko Nurvitadhi, Aravind Dasu, and Martin Langhammer, propose FlexScore as a flexibility metric based on the relationship between flexibility and goodness metrics, such as performance. Please contact Tian Tan and Derek Chiou (UT Austin).
March 2021 | The paper “FlexScore: Quantifying Flexibility” was accepted to Computer Architecture Letters. In the paper, Crossroads PIs and students, along with Intel co-authors Eriko Nurvitadhi, Aravind Dasu, and Martin Langhammer, propose FlexScore as a flexibility metric based on the relationship between flexibility and goodness metrics, such as performance. Please contact Tian Tan and Derek Chiou (UT Austin). (Read Less)
February 18th & 19th, 2021 | A formal kick-off meeting was held with Intel and VMware. Besides PI presentations, the meeting featured key Intel and VMware technology stakeholders sharing their visions for FPGA technologies in datacenters.
February 18th & 19th, 2021 | A formal kick-off meeting was held with Intel and VMware. Besides PI presentations, the meeting featured key Intel and VMware technology stakeholders sharing their visions for FPGA technologies in datacenters. (Read Less)
January 12th, 2021 | The center’s PIs and students got together for an all-day goal-setting workshop. The PIs layout plans for the center’s research vectors, and the students presented the technologies they bring to seed the center’s research. Many members of Intel and VMware were on-hand to participate. Going forward, we have plan to hold similar student-driven workshops bi-annually.
January 12th, 2021 | The center’s PIs and students got together for an all-day goal-setting workshop. The PIs layout plans for the center’s research vectors, and the students presented the technologies they bring to seed the center’s research. Many members of Intel and VMware were on-hand to participate. Going forward, we have plan to hold similar student-driven workshops bi-annually. (Read Less)
January 1st, 2021 | The Intel/VMware Crossroads 3D-FPGA Academic Research Center officially started underway, although the PIs and students have been working together for several months.
January 1st, 2021 | The Intel/VMware Crossroads 3D-FPGA Academic Research Center officially started underway, although the PIs and students have been working together for several months. (Read Less)