As a computing device, there is greater requirement for programmable flexibility—an FPGA will be asked to do more tasks than could fit on the fabric at once and to do new tasks that are unknown before deployment. Beyond flexibility, dynamically managing the logic resource utilization can be a means of performance optimization, by devoting available resources to only active tasks or by supporting tasks with differently-optimized design variants to changing conditions. To maximally exploit the benefits of FPGAs’ programmability, RV5 aims to make runtime reprogramming a regular mode of operation to enable dynamic and shared utilization of Crossroads 3D-FPGA resources. RV5 will develop a PR discipline where the PR regions follow fabric tile boundaries and their external interactions are restricted to NoC-carried timing-insensitive message passing. The discipline creates a decoupling abstraction to allow flexible dynamic resource scheduling in both spatial and temporal sharing multi-tenancy. RV5 has the goal to push programming dynamism from days and hours to the granularity limits allowed by technology and justified by the benefits.
RV5 PI: James C. Hoe