Abstract: This talk explores mapping deep learning workloads onto spatial dataflow accelerators, focusing on AMD's adaptive intelligent engine (AIE) architecture. AIE fabrics in Versal FPGAs and Ryzen NPUs deliver immense compute capabilities via software-programmable core arrays connected by shared memory and flexible networks-on-chip. However, efficiently utilizing these arrays remains challenging: existing programming models lean heavily on manual effort or simple greedy algorithms that frequently produce unroutable designs for complex dataflow graphs.

To overcome these limitations, we introduce an automated placement and routing (PnR) framework designed to navigate the heterogeneous interconnects of AIE arrays. We first outline the unique optimization and mapping challenges posed by this class of spatial architecture. Through an evaluation of 202 benchmarks, we demonstrate that our algorithms, ranging from optimal mixed-integer linear programming (MILP) to fast heuristic searches, yield a 99% mapping success rate and a 30% hardware runtime speedup over the baseline MLIR-AIE toolchain. Finally, we discuss our latest work on addressing scalability, evaluating the PnR framework on larger AIE arrays using a new PathFinder-based router. This router decouples the spatial routing graph from an independent resource accounting model to natively negotiate AIE-specific constraints like buffers, locks, and communication modes. Compared against the MILP router from our previous evaluation, the PathFinder router is ~1000x faster at the NPU scale and over 5000x faster on larger Versal devices.

Bio: James Yen is a second year MASc student in the ECE department at the University of Toronto under the supervision of Prof. Vaughn Betz. His research interest includes spatial hardware CAD and compiler design for accelerators. He recently finished an internship at the AMD Research and Development (RAD) group. He also received his BASc in Computer Engineering from the University of Toronto in 2024.

Abstract: FPGAs are uniquely positioned to accelerate such input-dependent streaming applications, such as in security and database analytics, whose optimal resource provisioning is workload dependent. Combining inherent programmability with hardware-class performance and efficiency, FPGAs can deliver workload-customized instantiations that achieve better resource efficiency than fixed-function ASICs designed for the worst-case. However, their adoption is limited by the slow and rigid hardware-centric toolchains. Design productivity tools such as High-Level Synthesis (HLS), critical to building parameterizable designs, struggle to generate efficient solutions for input-dependent dataflows. Furthermore, existing performance simulators remain too detailed, preventing them from scaling effectively to model input-dependent variations in real-world workloads.

In this talk, I will present my thesis work on accelerating input-dependent streaming pipelines on FPGAs. First, I will introduce a systematic methodology for representing input-dependent design patterns using the streaming paradigm in statically scheduled HLS. Applying this methodology, we generalized the string-matching filters from an RTL-based network intrusion detection accelerator into a reusable library and deployed it for Log Monitoring, achieving 200Gbps on a single FPGA-enabled server at one-quarter the cost of existing software solutions. Next, I will present RapidQ, a queuing-inspired performance modeling workflow. RapidQ leverages the structure imparted by the streaming paradigm in HLS to create a lightweight abstraction that decouples end-to-end performance from workload-dependent functionality. RapidQ achieves a 7x speedup over state-of-the-art simulators like LightningSim, and when integrated into an automated Design Space Exploration (DSE) flow, it effectively tunes module throughputs and buffer sizes to achieve up to 42% resource savings for real-world workloads.

Bio: Shashank Obla is an FPGA Architect at Altera. His research interests lie in next-generation reconfigurable architectures and systems. He received his Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University, advised by Prof. James C. Hoe and his B.Tech and M.Tech in Electrical Engineering from the Indian Institute of Technology, Bombay.