Abstract: This talk explores mapping deep learning workloads onto spatial dataflow accelerators, focusing on AMD's adaptive intelligent engine (AIE) architecture. AIE fabrics in Versal FPGAs and Ryzen NPUs deliver immense compute capabilities via software-programmable core arrays connected by shared memory and flexible networks-on-chip. However, efficiently utilizing these arrays remains challenging: existing programming models lean heavily on manual effort or simple greedy algorithms that frequently produce unroutable designs for complex dataflow graphs.

To overcome these limitations, we introduce an automated placement and routing (PnR) framework designed to navigate the heterogeneous interconnects of AIE arrays. We first outline the unique optimization and mapping challenges posed by this class of spatial architecture. Through an evaluation of 202 benchmarks, we demonstrate that our algorithms, ranging from optimal mixed-integer linear programming (MILP) to fast heuristic searches, yield a 99% mapping success rate and a 30% hardware runtime speedup over the baseline MLIR-AIE toolchain. Finally, we discuss our latest work on addressing scalability, evaluating the PnR framework on larger AIE arrays using a new PathFinder-based router. This router decouples the spatial routing graph from an independent resource accounting model to natively negotiate AIE-specific constraints like buffers, locks, and communication modes. Compared against the MILP router from our previous evaluation, the PathFinder router is ~1000x faster at the NPU scale and over 5000x faster on larger Versal devices.

Bio: James Yen is a second year MASc student in the ECE department at the University of Toronto under the supervision of Prof. Vaughn Betz. His research interest includes spatial hardware CAD and compiler design for accelerators. He recently finished an internship at the AMD Research and Development (RAD) group. He also received his BASc in Computer Engineering from the University of Toronto in 2024.

Abstract: The emergence of AI agents raises an intriguing question: can we fully automate the accelerator development process? While agentic software engineering has shown remarkable progress, directly extending existing approaches to hardware remains challenging. Unlike software, accelerator development is constrained by two major bottlenecks. First, current hardware design methodologies rely on costly modeling, synthesis, and implementation flows that can require hours to days for a single iteration. Second, each new accelerator often requires substantial manual effort to construct and optimize the accompanying software stack. Together, these bottlenecks fundamentally limit the rate at which designers and AI agents can explore the hardware-software co-design space.

This talk explores the hypothesis of autonomous accelerator design, and shares results and lessons learned from our recent work on (1) new abstractions that help unify accelerator design and programming, (2) differentiable compiler optimization, and (3) agentic approaches to compiler construction. I will discuss how these directions may collectively move us closer to a future of more autonomous accelerator design. I will discuss how these directions may collectively move us closer to a future of more autonomous accelerator design.

Bio: Zhiru Zhang is a Professor in the School of ECE at Cornell University. His current research investigates new algorithms, design methodologies, and automation tools for heterogeneous computing. Dr. Zhang is an IEEE Fellow and has been honored with the Intel Outstanding Researcher Award, AWS AI Amazon Research Award, Facebook Research Award, Google Faculty Research Award, DAC Under-40 Innovators Award, DARPA Young Faculty Award, IEEE CEDA Ernest S. Kuh Early Career Award, and NSF CAREER Award. He has also received 10+ best paper awards from premier conferences and journals in computer systems and EDA. He has founded or helped build several successful startups. Most notably, he co-founded AutoESL, an HLS startup acquired by Xilinx (now part of AMD). AutoESL's technology became Vivado HLS (now Vitis HLS), the most widely-used HLS tool for FPGA accelerator design.