Abstract: FPGAs are uniquely positioned to accelerate such input-dependent streaming applications, such as in security and database analytics, whose optimal resource provisioning is workload dependent. Combining inherent programmability with hardware-class performance and efficiency, FPGAs can deliver workload-customized instantiations that achieve better resource efficiency than fixed-function ASICs designed for the worst-case. However, their adoption is limited by the slow and rigid hardware-centric toolchains. Design productivity tools such as High-Level Synthesis (HLS), critical to building parameterizable designs, struggle to generate efficient solutions for input-dependent dataflows. Furthermore, existing performance simulators remain too detailed, preventing them from scaling effectively to model input-dependent variations in real-world workloads.

In this talk, I will present my thesis work on accelerating input-dependent streaming pipelines on FPGAs. First, I will introduce a systematic methodology for representing input-dependent design patterns using the streaming paradigm in statically scheduled HLS. Applying this methodology, we generalized the string-matching filters from an RTL-based network intrusion detection accelerator into a reusable library and deployed it for Log Monitoring, achieving 200Gbps on a single FPGA-enabled server at one-quarter the cost of existing software solutions. Next, I will present RapidQ, a queuing-inspired performance modeling workflow. RapidQ leverages the structure imparted by the streaming paradigm in HLS to create a lightweight abstraction that decouples end-to-end performance from workload-dependent functionality. RapidQ achieves a 7x speedup over state-of-the-art simulators like LightningSim, and when integrated into an automated Design Space Exploration (DSE) flow, it effectively tunes module throughputs and buffer sizes to achieve up to 42% resource savings for real-world workloads.

Bio: Shashank Obla is an FPGA Architect at Altera. His research interests lie in next-generation reconfigurable architectures and systems. He received his Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University, advised by Prof. James C. Hoe and his B.Tech and M.Tech in Electrical Engineering from the Indian Institute of Technology, Bombay.

Abstract: The emergence of AI agents raises an intriguing question: can we fully automate the accelerator development process? While agentic software engineering has shown remarkable progress, directly extending existing approaches to hardware remains challenging. Unlike software, accelerator development is constrained by two major bottlenecks. First, current hardware design methodologies rely on costly modeling, synthesis, and implementation flows that can require hours to days for a single iteration. Second, each new accelerator often requires substantial manual effort to construct and optimize the accompanying software stack. Together, these bottlenecks fundamentally limit the rate at which designers and AI agents can explore the hardware-software co-design space.

This talk explores the hypothesis of autonomous accelerator design, and shares results and lessons learned from our recent work on (1) new abstractions that help unify accelerator design and programming, (2) differentiable compiler optimization, and (3) agentic approaches to compiler construction. I will discuss how these directions may collectively move us closer to a future of more autonomous accelerator design. I will discuss how these directions may collectively move us closer to a future of more autonomous accelerator design.

Bio: Zhiru Zhang is a Professor in the School of ECE at Cornell University. His current research investigates new algorithms, design methodologies, and automation tools for heterogeneous computing. Dr. Zhang is an IEEE Fellow and has been honored with the Intel Outstanding Researcher Award, AWS AI Amazon Research Award, Facebook Research Award, Google Faculty Research Award, DAC Under-40 Innovators Award, DARPA Young Faculty Award, IEEE CEDA Ernest S. Kuh Early Career Award, and NSF CAREER Award. He has also received 10+ best paper awards from premier conferences and journals in computer systems and EDA. He has founded or helped build several successful startups. Most notably, he co-founded AutoESL, an HLS startup acquired by Xilinx (now part of AMD). AutoESL's technology became Vivado HLS (now Vitis HLS), the most widely-used HLS tool for FPGA accelerator design.