Abstract: Modern deep learning workloads increasingly rely on narrow numerical formats to improve efficiency and reduce memory footprint. The recently standardized microscaling floating point (MXFP) family of formats, including MXFP8, MXFP6, and MXFP4, offers a practical approach to low-precision inference, yet the digital signal processing (DSP) blocks in current FPGA architectures offer limited native support for these formats. In this work, we first present a comprehensive characterization of MXFP dot product implementations on Altera Agilex-5 FPGAs, exploring a range of strategies spanning pure soft logic, DSP blocks in fixed-point, floating-point, and tensor modes

Our results show that while the tensor mode delivers the highest arithmetic density for MXFP4 (E2M1) and MXFP6 (E2M3), it cannot implement MXFP6 (E3M2) or any MXFP8 precisions, forcing designers to fall back to lower-density alternatives. Motivated by this gap, we propose targeted modifications to the DSP block’s internal tensor-mode architecture that enable native support for all MXFP precisions while retaining backward compatibility. We estimate the area cost of these modifications using a simplified version of the Agilex-5 DSP block core implemented using the open-source ASAP7 PDK. We evaluate a variety of modified DSP block designs that present a tradeoff between format coverage, arithmetic density, and area overhead.

Our preferred design point increases the DSP tile area by 36%, corresponding to only 1.8% of the total FPGA die area. We evaluate the device-level impact of our enhanced DSP block by comparing systolic array matrix multiplier implementations across all MXFP precisions, contrasting the best-available strategies on the existing architecture against designs leveraging our modified DSP block. Our results demonstrate an average throughput improvement of 4.2× across all supported MXFP formats.

Bio: Marwan is an MASc student at the University of Waterloo under the supervision of Prof. Andrew Boutros. His research interests include computer architecture and reconfigurable computing, with a focus on the use of low-precision numerical formats for AI workloads on FPGAs. Prior to graduate school, Marwan worked as a Senior Silicon Design Engineer at AMD within the GPU team and received a BEng in Electrical and Biomedical Engineering from McMaster University. He is currently interning at Altera, where his work focuses on the development of soft IP for accelerating deep learning workloads.

Abstract: 2.5D FPGAs, which integrate multiple dice using interposers and 3D stacking enable larger capacity and better-yielding FPGA systems. However, they raise new questions about how to best extend the programmable interconnect beyond a single die in a way that is transparent to the end user. In this talk we present our work on modeling multi-die 2.5D and 3D FPGAs. We start from detailed circuit models that account for the intricate details of the silicon and the packaging technology, which gives us accurate area and delay values for inter-die connectivity. We then present our FPGA modelling and specification approach, which enhances the VTR open-source FPGA CAD flow to support modelling a wide range of multi-die FPGAs. Finally, we overview the associated CAD challenges with multi-die FPGAs and present our solutions. We use our multi-die enhanced VTR to perform a comprehensive study of many different multi-die FPGA architectures, highlighting various pitfalls of a multi-die FPGA architecture and the many trade-offs that exist. With well-designed multi-die FPGAs and multi-die-aware CAD algorithms, we show that using existing and mature 2.5D and 3D packaging technologies, 3D FPGAs outperform their 2D counterparts in both area and delay, while 2.5D FPGAs can achieve delay equivalent to 2D ones with only 1% to 3% more area, with greatly improved yield.

Bio: Amir Poolad is a second-year MASc student in the ECE department at the University of Toronto under the supervision of Prof. Vaughn Betz. He is a maintainer of the VTR open-source FPGA CAD flow and his research interests are the intersection of FPGA architecture and CAD and how emergent chip manufacturing technologies affect reconfigurable hardware. He received his BSc degree in Computer Engineering from Amir Kabir University of Technology (Tehran Polytechnic) in 2024.