Intel/VMware Crossroads 3D-FPGA Academic Research Center

Field Programmable Gate Arrays (FPGAs) have been undergoing rapid and dramatic changes fueled by their expanding use in datacenter computing. Rather than serving as a compromise or alternative to ASICs, FPGA ‘programmable logic’ is emerging as a third paradigm of compute that stands apart from traditional hardware vs. software archetypes. A multi-university, multi-disciplinary team has been formed behind the question:

What should be the future role of FPGAs as a central function in datacenter servers?

Guided by both the demands of modern networked, data-centric computing and the new capabilities from 3D integration, the Intel/VMware Crossroads 3D-FPGA Academic Research Center will investigate a new programmable hardware data-nexus lying at the heart of the server and operating over data ‘on the move’ between network, traditional compute, and storage elements.

The Intel/VMware Crossroads 3D-FPGA Academic Research Center is jointly supported by Intel and VMware. The center is committed to public and free dissemination of its research outcome.

Upcoming Seminars

Thursday, June 25, 2026 | 11AM~12PM ET | SFB 560

Zoom

Arch + EDA Co-Design in Modern FPGA Systems
Rachel Selina Rajarathnam, AMD

Abstract: This talk presents an industry perspective on the evolution of AMD-Xilinx FPGAs, from the XC2064 to modern Versal adaptive SoCs, highlighting broader trends in digital system design. Across technology nodes, FPGA fabrics have advanced through increasing architectural regularity, greater heterogeneity, and selective hardening of functions such as DSP, memory, and high-speed I/O. As Moore’s Law slows, FPGA design faces growing constraints from reticle limits, advanced-node scaling challenges, power density, and yield. In response, the industry increasingly relies on innovations in heterogeneous packaging, architecture, and software tools to extend system capacity and bandwidth. Using routing as a case study, the talk shows how co-design of FPGA architecture and EDA can deliver significant improvements in quality of results and runtime compared with hardware-only or software-only enhancements. Finally, AMD-Xilinx FPGA EDA contests are highlighted as a practical entry point into industrial placement, routing, and optimization problems.

Bio: Rachel Selina Rajarathnam is currently a Senior Staff Engineer on the FPGA Fabric Architecture Team at AMD. She received her Ph.D. in Electrical and Computer Engineering from the University of Texas at Austin, advised by Prof. David Z. Pan. Most of her doctoral research focused on FPGA placement algorithms and acceleration. Prior to her Ph.D., Rachel worked in the ASIC physical design team at NVIDIA and has also interned with the FPGA placer team at Intel/Altera. She is a Senior IEEE Member with research interests in FPGA fabric architecture and physical design.

[Find all Seminars here]

FPGA Technology at Crossroads