The Crossroads seminar series is offered regularly on Fridays 2~3pm (US eastern). The seminar series will feature the latest research results by the center's PIs and students, as well as a diverse range of talks including informal work-in-progress and invited outside speakers.
How hard is it to use an FPGA for compute acceleration in 2023?
James C. Hoe,
Carnegie Mellon University
CAD and Architecture Exploration Tools for Next-Generation Reconfigurable Acceleration Devices
Andrew Boutros,
University of Toronto
Terminus: Moving the Center of Cloud Servers from Cores to SmartNICs and Beyond
Derek Chiou,
The University of Texas at Austin
Re-envisioning generic server architectures for I/O-driven compute
Justine Sherry,
Carnegie Mellon University
Capturing Realistic Architectures for Field Programmable Gate Array Optimization
Kimia Talaei,
University of Toronto
CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture
Peipei Zhou,
University of Pittsburgh
Vela: Host-Side Uniform Programming Platform for Network Processing
Jiaqi Gao,
Alibaba Group US
The Future of Computing Beyond Moore’s Law
John Shalf,
Lawrence Berkeley National Laboratory
Groq’s Software-Defined Hardware for Dataflow Compute
Andrew Bitar,
Groq
HPIPE-NX: Leveraging Tensor Blocks for High-Performance CNN Inference Acceleration on FPGAs
Marius Stan,
University of Toronto
Efficient, Programmable, and Manufacturable Hardware: The Case for Synthesizable FPGAs
Ang Li,
Princeton University
OverGen: Improving FPGA Usability through Domain-specific Overlay Generation
Tony Nowatzki,
University of California at Los Angelos
RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices
Andrew Boutros,
University of Toronto
FPGA-Predict: Performance and Power Prediction of FPGAs Using Machine Learning and Application Characteristics
Lina Sawalha,
Western Michigan University
Soft NOC: Leveraging HyperFlex and Long Wires to Construct High-Performance Pipelined Busses
Scott Weber,
Intel
Soft Embedded FPGA Fabrics: Top-down Physical Design and Applications
Prashanth Mohan,
Carnegie Mellon University
FPGAs are (not) Good at Deep Learning
Mohamed S. Abdelfattah,
Cornell University
Near-Storage Acceleration in Practice: Opportunities and Challenges
Sang-Woo Jun,
University of California, Irvine
High Performance CNN Inference Acceleration on FPGAs
Mohamed Ibrahim,
University of Toronto
Re-thinking Data Center Hardware Architectures from the Ground-up
Akshitha Sriraman,
Carnegie Mellon University
Redesigning NIC Interfaces for Direct Application Access
Hugo Sadok,
Carnegie Mellon University
Towards Predictable and Efficient Datacenter Storage
Huaicheng Li,
Carnegie Mellon University
Unleashing the Potential of In-Network Computing
Daehyeok Kim,
Microsoft
SurgeProtector: Mitigating Algorithmic Complexity Attacks using Adversarial Scheduling
Nirav Atre,
Carnegie Mellon University
In this talk, I will present a general framework we designed to make any NF more resilient to ACAs without the limitations of prior approaches. Our framework, SurgeProtector, uses the NF's scheduler to mitigate the impact of ACAs using a very traditional scheduling algorithm---Weighted Shortest Job First (WSJF). To evaluate SurgeProtector, we propose a new metric of DoS vulnerability called the Displacement Factor (DF), which quantifies the maximum "harm per unit effort" an adversary can inflict on the system. Using novel insights from adversarial scheduling theory, we show that any system using WSJF has a worst-case DF of only a small constant (unity), where traditional schedulers would place no upper bound on the adversary's DF. Illustrating that SurgeProtector is not only theoretically, but practically robust, we integrate SurgeProtector into an open source Intrusion Detection System (IDS). Under simulated attack, the SurgeProtector-augmented IDS suffers 90-99% lower innocent traffic loss than the original system.
It is All About Abstraction: Virtualizing FPGAs in the Cloud
Jing Li,
University of Pennsylvania
In this talk, I will present our exploratory efforts to address these limitations. I will first present the key requirements that we identified for virtualizing spatial architecture and present a generic virtualization stack that satisfies the requirements for heterogeneous FPGA clusters. Specifically, I will introduce a two-level system abstraction that can decouple the compilation and resource allocation and thus enables fine-grained resource management with low compilation overhead. I will present how we modify existing compilation flow and runtime management to leverage the proposed abstraction to achieve efficient virtualization. Finally, I will discuss further optimization opportunities through two case studies.
AIgean: An Open Framework for Deploying Machine Learning on Heterogeneous Clusters
Naif Tarafdar and Paul Chow,
University of Toronto
Paul Chow is a professor in the faculty of The Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the University of Toronto. He is a Fellow of the IEEE and Fellow of the Engineering Institute of Canada. His main research is about making FPGAs into computing devices so that applications can be easily deployed. In particular, he wants to do this at scale in a heterogeneous environment where FPGAs seamlessly interact with CPUs and other devices, all as peers, and transparently to the application.
FPGA Placement: Recent Progress and Road Ahead
David Z. Pan,
The University of Texas at Austin
Crossroads RV1: Exploring Data on the Move Applications
Justine Sherry,
Carnegie Mellon University
Verilog to Routing (VTR): A Flexible Open-Source CAD Flow to Explore and Target Diverse FPGA Architectures
Vaughn Betz,
University of Toronto
From “Field Programmable” to “Programmable”
James C. Hoe,
Carnegie Mellon University
Pigasus: Efficient Handling of Input-Dependent Streaming on FPGAs
Zhipeng Zhao,
Carnegie Mellon University
Soft Processor Overlays to Improve Time-to-Solution
Derek Chiou,
The University of Texas at Austin
High-Performance Code Generation for Graph Applications
Sanil Rao,
Carnegie Mellon University
We Need Kernel Interposition over the Network Dataplane
Hugo Sadok,
Carnegie Mellon University
The Role for Programmable Logic in Future Datacenter Servers
(An Overview of the Crossroads Center)
James C. Hoe,
Carnegie Mellon University
Raising the Level of Abstraction for FPGA System Design
Joseph Melber,
Carnegie Mellon University